Imagination:JD - MIPS Hardware Design Engineer (RTL+DV)

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Joined: 2016-03-15
Position:Hardware Design Engineer

Sector: HW2 (CEC)
Location: Shanghai, China
Date Issued:8/19/2016

The Role:

Imagination Technologies is one of the world’s fastest growing and most exciting technology companies. Rapidly climbing the FTSE250 on the London Stock Exchange, the breadth of technologies and markets it serves involves working with most of the biggest and best semiconductor, consumer electronics, multimedia and App content developers and industry partners in the world. Our technologies feature in many of the world’s most exciting products, from the latest smartphones, tablets and media players to the future wireless home, connected multimedia-rich cars and much more.
Situated in Shanghai, the China-Engineering-Center MIPS hardware group is responsible for developing and promoting the M-class product line which includes 4 to 6 stage pipeline microcontrollers and microprocessors.
RTL designer primarily, mainly focus on MIPS lower class cores such as M14K/MicroAptiv/Virtuo/Viking, and so on. Also, works as a complementary if other engineers are busy with the inter class cores.

Reports To:

Bo Zhou

Direct Reports:


Travel Requirements:

None expected. Though, upon project needs, optional travel to US office may be recommended.


As a part of the M-class design team, you will be working on the planning and implementation of the next-generation of micro-controllers and micro-processors. Furthermore, you will be discussing latest MIPS architecture and verification techniques with other experts in the field. You will be expected to contribute effort to the other team like DV and backend to aid them solving various issues.


You will be the expert of MIPS M-class cores and MIPS DV environment. You will also have opportunities to be familiar with higher end MIPS cores, such as I-class cpu.
Working as a part of a team, you will have some or all of the following responsibilities:
• Microarchitecture planning and design
• RTL design implementation including, but not limited to: CPU, peripherals, bus fabrics
• Frequency Speed, Area, Power, Performance analysis and closure
• Open discussion, presentation, documentation
• Describe and/or develop test plans and testbenches to aid verification work
• Familiar with MIPS ISA and AVP environment to aid test case failure debugging work

Required Skills:

• In-depth experience with RISC CPU and pipeline concepts
• Strong communications skills and capability to describe in detail all aspects of a design
• STA, Area report, performance pipegraph, power report analysis and optimization techniques
• Assembly language knowledge and writing skills
• Linux/Csh/Tcsh/Tk/Perl and/or other scripting language usage
• Synopsys/Cadence/Mentor tool usage and waveform analysis
• Knowledge of SOC/FPGA design is welcome

Desirable Skills:

• MIPS CPU knowledge
• Verbal and written English competency
• RTL/testbenches writing skills

Personal Attributes / Characteristics /:

The successful candidate will have:
• Self-starter – able to work both alone and as part of a team
• “Can-Do” approach to workload,
• Friendly - outgoing personality, gets on with all types of people
• Tenacious - determined not to let anything stop getting the job done
• Open - enjoys working in an informal environment
• Dedicated - willingness to work from time to time over extended hours in order to achieve goals set by immediate manager or demanded by business
• A passion for excellence and attention to detail
• Team player

Working Environment:

Fully understanding of MIPS architecture, M-class CPU RTL, including M14K/MicroAptiv/Virtuso/Viking, and so on. Capability of AVP/MVP/MRVP/SRVP testcases failure debugging. Providing ideas on how to resolve timing/area/power issues.


Fully understanding of MIPS architecture, M-class CPU RTL, including M14K/MicroAptiv/Virtuso/Viking, and so on. Capability of AVP/MVP/MRVP/SRVP testcases failure debugging. Providing ideas on how to resolve timing/area/power issues.

Key Words ;

CPU, MicroArchitecture, MIPS, RTL, pipeline, Synthesis, verification.

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