【MIPS CPU 体系结构概述2】连载8:

/* 中断初始化,核心的数据结构就是irq_desc[]数组
它的每个元素对应一个中断,记录该中断的控制器类型,处理函数,状态等 关于这些可以参见对x86中断的分析*/

void __init init_IRQ(void)
{
Bonito;

/*
* Mask out all interrupt by writing "1" to all bit position in * the interrupt reset reg.

*/

BONITO_INTEDGE = BONITO_ICU_SYSTEMERR | BONITO_ICU_MASTERERR | BONITO_ICU_RETRYERR | BONITO_ICU_MBOXES;
BONITO_INTPOL = (1 << (P6032INT_UART1-16)) | (1 << (P6032INT_ISANMI-16))
| (1 << (P6032INT_ISAIRQ-16))
| (1 << (P6032INT_UART0-16));

BONITO_INTSTEER = 0;
BONITO_INTENCLR = ~0;
/* init all controllers */
init_generic_irq();
init_i8259_irqs();
bonito_irq_init(16);

BONITO_INTSTEER |= 1 << (P6032INT_ISAIRQ-16);
BONITO_INTENSET = 1 << (P6032INT_ISAIRQ-16);
/* hook up the first-level interrupt handler */
set_except_vector(0, p6032IRQ);

}

/*p6032IRQ发现一个bonito中断后调用这个*/
asmlinkage void

bonito_irqdispatch(struct pt_regs *regs)
{
Bonito;

int irq;
unsigned long int_status;
int i;

/* Get pending sources, masked by current enables */ /*

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