【MIPS CPU 体系结构概述2】连载7:

/* p6032也使用8259来处理一些pc style的设备*/

jal i8259A_irqdispatch /* 调用8259控制器的中断分派代码*/

move a0, sp # delay slot

j ret_from_irq

nop # delay slot

1: beq a0, zero, 1f

andi a0, s0, CAUSEF_IP5

/* Wheee, bonito interrupt. */

/* bonito是6032板的北桥,它提供了一个中断控制器*/

jal bonito_irqdispatch

move a0, sp # delay slot

j ret_from_irq

nop # delay slot

1: beqz a0,1f

nop

/* Wheee, a debug interrupt. */

jal p6032_debug_interrupt

move a0, sp # delay slot

j ret_from_irq

nop # delay slot

1:
/* Here by mistake? This is possible, what can happen
* is that by the time we take the exception the IRQ
* pin goes low, so just leave if this is the case.
*/
j ret_from_irq
nop
END(p6032IRQ)

irq.c部分代码如下:

p6032中断共有四类:
begin{enumerate}
item timer中断,单独处理
item debug中断,单独处理
item 8259中断,由8259控制器代码处理
item bonito中断由bonito控制器代码处理 end{enumerate}

/* now mips kernel is using the same abstraction as x86 kernel,
that is, all irq in the system are described in an struct
array: irq_desc[]. Each item of a specific item records
all the information about this irq,including status,action,
and the controller that handle it etc. Below is the controller
structure for bonito irqs,we can easily guess its functionality
from its names.*/
hw_irq_controller bonito_irq_controller = {
"bonito_irq",
bonito_irq_startup,
bonito_irq_shutdown,
bonito_irq_enable,
bonito_irq_disable,
bonito_irq_ack,
bonito_irq_end,

NULL /* no affinity stuff for UP */
};

void
bonito_irq_init(u32 irq_base)
{
extern irq_desc_t irq_desc[];
u32 i;
for (i= irq_base; i< P6032INT_END; i++) {
irq_desc[i].status = IRQ_DISABLED;
irq_desc[i].action = NULL;
irq_desc[i].depth = 1;
irq_desc[i].handler = &bonito_irq_controller;
}

bonito_irq_base = irq_base;
}

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