【MIPS CPU 体系结构概述2】连载6:

irq.c部分代码如下:

p6032中断共有四类:

begin{enumerate}
item timer中断,单独处理
item debug中断,单独处理
item 8259中断,由8259控制器代码处理
item bonito中断由bonito控制器代码处理 end{enumerate}

/* now mips kernel is using the same abstraction as x86 kernel,
that is, all irq in the system are described in an struct
array: irq_desc[]. Each item of a specific item records
all the information about this irq,including status,action,
and the controller that handle it etc. Below is the controller
structure for bonito irqs,we can easily guess its functionality
from its names.*/

hw_irq_controller bonito_irq_controller = {
"bonito_irq",
bonito_irq_startup,
bonito_irq_shutdown,
bonito_irq_enable,
bonito_irq_disable,
bonito_irq_ack,
bonito_irq_end,
NULL /* no affinity stuff for UP */
};

void
bonito_irq_init(u32 irq_base)
{
extern irq_desc_t irq_desc[];
u32 i;
for (i= irq_base; i< P6032INT_END; i++) {
irq_desc[i].status = IRQ_DISABLED;
irq_desc[i].action = NULL;
irq_desc[i].depth = 1;
irq_desc[i].handler = &bonito_irq_controller;
}

bonito_irq_base = irq_base;
}

/* 中断初始化,核心的数据结构就是irq_desc[]数组
它的每个元素对应一个中断,记录该中断的控制器类型,处理函数,状态等 关于这些可以参见对x86中断的分析*/

void __init init_IRQ(void)
{
Bonito;

/*
* Mask out all interrupt by writing "1" to all bit position in * the interrupt reset reg.
*/

BONITO_INTEDGE = BONITO_ICU_SYSTEMERR | BONITO_ICU_MASTERERR | BONITO_ICU_RETRYERR | BONITO_ICU_MBOXES;
BONITO_INTPOL = (1 << (P6032INT_UART1-16)) | (1 << (P6032INT_ISANMI-16))
| (1 << (P6032INT_ISAIRQ-16))
| (1 << (P6032INT_UART0-16));

BONITO_INTSTEER = 0;
BONITO_INTENCLR = ~0;
/* init all controllers */
init_generic_irq();
init_i8259_irqs();
bonito_irq_init(16);

BONITO_INTSTEER |= 1 << (P6032INT_ISAIRQ-16);
BONITO_INTENSET = 1 << (P6032INT_ISAIRQ-16);
/* hook up the first-level interrupt handler */
set_except_vector(0, p6032IRQ);

}

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