【MIPS CPU 体系结构概述2】连载5:

下面列出这两个文件以便解说:

p6032IRQ.s
algor p6032(笔者用的开发板)中断安排如下: MIPS IRQ Source
*
* 0 Software (ignored)
* 1 Software (ignored)
* 2 bonito interrupt (hw0)
* 3 i8259A interrupt (hw1)
* 4 Hardware (ignored)
* 5 Debug Switch
* 6 Hardware (ignored)
* 7 R4k timer (what we use)

.text
.set noreorder
.set noat
.align 5
NESTED(p6032IRQ, PT_SIZE, sp)

SAVE_ALL /* 保存现场,切换堆栈(if usermode -> kernel mode)*/

CLI /* 关中断,mips有多种方法禁止响应中断,CLI用清status相应位 的方法,如下: Move to kernel mode and disable interrupts. Set cp0 enable bit as sign
that we're running on the kernel stack */

#define CLI
mfc0 t0,CP0_STATUS;
li t1,ST0_CU0|0x1f;
or t0,t1;
xori t0,0x1f;
mtc0 t0,CP0_STATUS

.set at

mfc0 s0, CP0_CAUSE
/* get irq mask,中断响应时cause寄存器指示 哪类中断发生注意,MIPS CPU只区分8个中断源,并没有象 PC中从总线读取中断向量号,所以每类中断 的代码要自己设法定位中断 */

/* 挨个检查可能的中断原因 */
/* First we check for r4k counter/timer IRQ. */ andi a0, s0, CAUSEF_IP7
beq a0, zero, 1f
andi a0, s0, CAUSEF_IP3
/* Wheee, a timer interrupt. */
li a0, 63
jal do_IRQ
move a1, sp
j ret_from_irq

# delay slot, check 8259 interrupt

nop # delay slot

1: beqz a0,1f

andi a0, s0, CAUSEF_IP2

/* Wheee, i8259A interrupt. */

/* p6032也使用8259来处理一些pc style的设备*/

jal i8259A_irqdispatch /* 调用8259控制器的中断分派代码*/

move a0, sp # delay slot

j ret_from_irq

nop # delay slot

1: beq a0, zero, 1f

andi a0, s0, CAUSEF_IP5

/* Wheee, bonito interrupt. */

/* bonito是6032板的北桥,它提供了一个中断控制器*/

jal bonito_irqdispatch

move a0, sp # delay slot

j ret_from_irq

nop # delay slot

1: beqz a0,1f

nop

/* Wheee, a debug interrupt. */

jal p6032_debug_interrupt

move a0, sp # delay slot

j ret_from_irq
nop # delay slot

1:
/* Here by mistake? This is possible, what can happen
* is that by the time we take the exception the IRQ
* pin goes low, so just leave if this is the case.
*/
j ret_from_irq
nop
END(p6032IRQ)

--电子创新网--
粤ICP备12070055号